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Chapter 6. BUFFER MEMORY AND I/O SIGNAL CONFIGURATON
2) Output signals: PLC CPU module à High Speed Counter module
S i g n a l
P(N+1)0
P(N+1)1
P(N+1)2
P(N+1)3
P(N+1)4
P(N+1)5
P(N+1)6
P(N+1)7
P(N+1)8
P(N+1)9
P(N+1)A
P(N+1)B
P(N+1)C
P(N+1)D
P(N+1)E
P(N+1)F
※ ' N ' means the I/O word number of the High Speed Counter module.
C o n t e n t s
Counter Preset Signal
Counter Set Signal
Counter operation enable signal
Increment/decrement count specification signal
Output enable signal
Home Latch enable signal
Coincidence rest signal
Carry/Borrow Reset Signal
Counter Preset Signal
Counter Set Signal
Counter operation enable signal
Increment/decrement count specification signal
Output enable signal
Home Latch enable signal
Coincidence rest signal
Carry/Borrow Reset Signal
6 - 4
Remarks
Channel 0
Channel 1
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Troubleshooting
