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Chapter 6. BUFFER MEMORY AND I/O SIGNAL CONFIGURATON
6.1 Operating block diagram
1 )
G 3 F - H S C A
P h a s e
P h a s e
A
※ The above shows the operation block diagram where the I/O word number of the G3F-HSCA is
0
G 3 F - H S C A
P h a s e
B
Z
T e r m i n a l B l o c k
Buffer
s e n d / r e c e i v e b y P U T / G E T .
Preset
Increment/Decrement Count
Set
Counter Preset Signal
P L C → H S C
H S C →
Counter Operation Enable
P L C
Increment/Decrement Count
Specification Signal
Output Enable Signal
Home Latch Signal
Coincidence Reset Signal
C a r r y / B o r r o w R e s e t S i g n a l
6 - 1
PLC CPU
Memory
data
O U T 1
O U T 2
Home Input
C a r r y S i g n a l
B o r r o w S i g n a l
Data Format Error
Counter Set Signal
Signal
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