Epson S5U13706P00C100 User Manual
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S1D13706 Embedded Memory LCD Controller
S5U13706P00C100 Evaluation Board
User Manual
Document Number: X31B-G-021-01
Status: Revision 1.1
Issue Date: 2009/03/03
© SEIKO EPSON CORPORATION 2007 - 2009. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Revision 1.1
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Table of Contents
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Summary of Contents for Epson S5U13706P00C100
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Page 1: User Manual
The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners Revision 1.1... - Page 2 Page 2 Epson Research and Development Vancouver Design Center S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1...
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Page 3: Table Of Contents
11 Technical Support ........28 11.1 EPSON LCD Controllers (S1D13706) ..... 28... -
Page 4: Vancouver Design Center
Page 4 Epson Research and Development Vancouver Design Center S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1... -
Page 5: Introduction
Board. The board is designed as an evaluation platform for the S1D13706 Embedded Memory LCD Controller. This user manual is updated as appropriate. Please check the Epson Research and Devel- opment website at www.erd.epson.com for the latest revision of this document before beginning any development. -
Page 6: Features
Epson Research and Development Vancouver Design Center 2 Features Following are some features of the S5U13706P00C100 Evaluation Board: • 100-pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of embedded SRAM. • Headers for connecting to various Host Bus Interfaces. -
Page 7: Installation And Configuration
Vancouver Design Center 3 Installation and Configuration The S5U13706P00C100 is designed to support as many platforms as possible. The S5U13706P00C100 incorporates a DIP switch and three jumpers which allow both the evaluation board and S1D13706 LCD controller to be configured for a specified evaluation platform. - Page 8 • GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1b. • GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0b. • Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1b. S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1...
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Page 9: Configuration Jumpers
HR-TFT and D-TFD panels as GPIO0 is required for both panels. For details, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. GPIO0 connected GPIO0 disconnected... - Page 10 Position 1-2 sets the voltage level to 5.0V. Position 2-3 sets the voltage level to 3.3V (default setting). Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. 5.0V 3.3V...
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Page 11: Cpu Interface
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. These pins are not used in their corresponding Host Bus Interface mode. Systems are responsible for externally connecting them to the host interface IO V S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1... -
Page 12: Cpu Bus Connector Pin Mapping
Connected to WE0# of the S1D13706 Connected to WAIT# of the S1D13706 Connected to CS# of the S1D13706 Connected to MR# of the S1D13706 Connected to WE1# of the S1D13706 Connected to TXVDD1 S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1... - Page 13 Connected to RD/WR# of the S1D13706 Connected to BS# of the S1D13706 Connected to BUSCLK of the S1D13706 Connected to RD# of the S1D13706 Not connected Not connected S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...
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Page 14: Lcd Interface Pin Mapping
GPO on H1 can be inverted by setting JP4 to 2-3. The Sharp HR-TFT MOD signal controls the panel power. This must not be confused with the MOD signal used on many passive panels. S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1... - Page 15 If REG[10h] bits 1-0 are set for either HR-TFT or D-TFD, some of the pins are used for the HR-TFT or D-TFD interfaces and are not available as GPIO pins. S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...
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Page 16: Technical Description
PCI Bridge FPGA to support the PCI bus. 6.2 Direct Host Bus Interface Support The S5U13706P00C100 is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment. However, the S1D13706 directly supports many other host bus interfaces. -
Page 17: Passive/Active Lcd Panel Support
Extended LCD Connector, H2. For connection information, see Section 5, “LCD Interface Pin Mapping” on page 14. The S5U13706P00C100 does not provide a power supply for the LCD bias voltage needed by passive LCD panels. An external power supply is required to provide the bias LCD voltage to the LCD panel. -
Page 18: References
7 References 7.1 Documents • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, document number X31B-G-003-xx. 7.2 Document Sources • Epson Research and Development: http://www.erd.epson.com. -
Page 19: Parts List
Shielded SMT power Do not purchase. Do not L2, L1 47uH inductor, +/-20%, 1.17A, populate. 0.18 ohm Do not purchase. Do not MMBT3906 PNP Transistor / SOT-23 populate. S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1... - Page 20 5V fixed voltage regulator, Do not purchase. Do not LT1117CST-5 SOT-223 populate. TI 74AHC04, SO-14 74AHC04 SO-14 package package Do not purchase. Do not ICD2061A Wide SO-16 package populate. S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1...
- Page 21 2-3 of 0ohm JP2 and JP3 Epson SG8002DB, (U6) 50MHz Oscillator DIP14, 50MHz 50MHz, socketed Epson SG8002DB, (U5) 6.5MHz Oscillator DIP14, 6.5MHz 6.5MHz, socketed S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...
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Page 22: Schematics
Page 22 Epson Research and Development Vancouver Design Center 9 Schematics Figure 9-1: S5U13706P00C100 Schematics (1 of 5) S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1... - Page 23 Epson Research and Development Page 23 Vancouver Design Center Figure 9-2: S5U13706P00C100 Schematics (2 of 5) S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...
- Page 24 Page 24 Epson Research and Development Vancouver Design Center Figure 9-3: S5U13706P00C100 Schematics (3 of 5) S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1...
- Page 25 Epson Research and Development Page 25 Vancouver Design Center Figure 9-4: S5U13706P00C100 Schematics (4 of 5) S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...
- Page 26 Page 26 Epson Research and Development Vancouver Design Center Figure 9-5: S5U13706P00C100 Schematics (5 of 5) S1D13706 S5U13706P00C100 Evaluation Board User Manual X31B-G-021-01 Issue Date: 2009/03/03 Revision 1.1...
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Page 27: Board Layout
Epson Research and Development Page 27 Vancouver Design Center 10 Board Layout Figure 10-1: S5U13706P00C100 Board Layout S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1... -
Page 28: Technical Support
20/F, Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. - Page 29 • section 11 - update sales office addresses X31B-G-021-01 Revision 1.0 - Issued: March 19, 2007 • initial draft • minor edits • added parts list • added schematics • updated tech support contact information S5U13706P00C100 Evaluation Board User Manual S1D13706 Issue Date: 2009/03/03 X31B-G-021-01 Revision 1.1...