LG 43LF5100 Service Manual page 22
Hide thumbs
Also See for 43LF5100:
- Owner's manual (45 pages) ,
- Service manual (68 pages) ,
- Easy setup manual (51 pages)
Advertisement
+1.5V_DDR
+1.5V_DDR
CLose to DDR3
CLose to MAIN IC
DDR_EXT
DDR_EXT
R1201
R1204
1K
1K
1%
1%
A-MVREFDQ
DDR_EXT
DDR_EXT
DDR_EXT
DDR_EXT
DDR_EXT
DDR_EXT
R1202
C1201
C1202
R1205
C1213
C1214
1K
0.1uF
1000pF
1K
0.1uF
1000pF
1%
1%
DDR_1600_1G_NAN
DDR_1600_2G_SS
IC1201-*1
IC1201-*2
NT5CB64M16FP-DH
K4B2G1646Q-BCK0
EAN61859502
EAN61848803
N3
M8
N3
A0
VREFCA
A0
P7
P7
A1
A1
P3
P3
A2
A2
N2
H1
N2
A3
VREFDQ
A3
P8
P8
P2
A4
P2
A4
A5
A5
R8
L8
R8
A6
ZQ
A6
R2
R2
A7
A7
T8
T8
A8
A8
R3
B2
R3
A9
VDD_1
A9
L7
D9
L7
A10/AP
VDD_2
A10/AP
R7
G7
R7
A11
VDD_3
A11
N7
K2
N7
A12
VDD_4
A12/BC
T3
K8
T3
NC_6
VDD_5
A13
N1
VDD_6
M7
N9
M7
NC_5
VDD_7
NC_5
R1
VDD_8
M2
R9
M2
N8
BA0
VDD_9
N8
BA0
BA1
BA1
M3
M3
BA2
BA2
A1
VDDQ_1
J7
A8
J7
CK
VDDQ_2
CK
K7
C1
K7
CK
VDDQ_3
CK
K9
C9
K9
CKE
VDDQ_4
CKE
D2
VDDQ_5
L2
E9
L2
CS
VDDQ_6
CS
K1
F1
K1
ODT
VDDQ_7
ODT
J3
H2
J3
RAS
VDDQ_8
RAS
K3
H9
K3
CAS
VDDQ_9
CAS
L3
L3
WE
WE
J1
T2
NC_1
J9
T2
RESET
NC_2
RESET
L1
NC_3
L9
NC_4
F3
T7
F3
DQSL
NC_7
DQSL
G3
G3
DQSL
DQSL
C7
A9
C7
DQSU
VSS_1
DQSU
B7
B3
B7
DQSU
VSS_2
DQSU
E1
VSS_3
E7
G8
E7
DML
VSS_4
DML
D3
J2
D3
DMU
VSS_5
DMU
J8
VSS_6
E3
M1
E3
DQL0
VSS_7
DQL0
F7
M9
F7
DQL1
VSS_8
DQL1
F2
P1
F2
DQL2
VSS_9
DQL2
F8
P9
F8
DQL3
VSS_10
DQL3
H3
T1
H3
DQL4
VSS_11
DQL4
H8
T9
H8
DQL5
VSS_12
DQL5
G2
G2
DQL6
DQL6
H7
H7
DQL7
DQL7
B1
VSSQ_1
D7
B9
D7
DQU0
VSSQ_2
DQU0
C3
D1
C3
DQU1
VSSQ_3
DQU1
C8
D8
C8
DQU2
VSSQ_4
DQU2
C2
E2
C2
DQU3
VSSQ_5
DQU3
A7
E8
A7
DQU4
VSSQ_6
DQU4
A2
F9
A2
DQU5
VSSQ_7
DQU5
B8
G1
B8
DQU6
VSSQ_8
DQU6
A3
G9
A3
DQU7
VSSQ_9
DQU7
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
+1.5V_DDR
Option : Ripple Check !!!
A-MVREFCA
OPT
OPT
OPT
OPT
OPT
OPT
OPT
C1216
C1217
C1218
C1219
C1220
C1221
C1222
C1223
10uF
0.1uF
0.1uF
1uF
1uF
1uF
1uF
10V
A-MVREFCA
DDR_1600_2G_SK
IC1201-*3
H5TQ2G63FFR-PBC
A-MVREFDQ
EAN61829204
DDR_EXT
M8
N3
M8
VREFCA
A0
VREFCA
R1203
P7
A1
P3
A2
240 1%
H1
N2
H1
VREFDQ
A3
VREFDQ
+1.5V_DDR
P8
P2
A4
A5
L8
R8
L8
ZQ
A6
ZQ
R2
A7
T8
A8
B2
R3
B2
VDD_1
A9
VDD_1
D9
L7
D9
VDD_2
A10/AP
VDD_2
G7
R7
G7
VDD_3
A11
VDD_3
DDR_EXT
C1203
10uF 10V
K2
N7
K2
VDD_4
A12/BC
VDD_4
K8
T3
K8
DDR_EXT
C1204
0.1uF
VDD_5
A13
VDD_5
N1
N1
VDD_6
VDD_6
N9
M7
N9
VDD_7
NC_5
VDD_7
DDR_EXT
C1205
0.1uF
R1
R1
VDD_8
VDD_8
R9
M2
R9
DDR_EXT
C1206
0.1uF
VDD_9
N8
BA0
VDD_9
BA1
M3
C1207
0.1uF
BA2
DDR_EXT
A1
A1
VDDQ_1
VDDQ_1
A8
J7
A8
VDDQ_2
CK
VDDQ_2
DDR_EXT
C1208
0.1uF
C1
K7
C1
VDDQ_3
CK
VDDQ_3
C9
K9
C9
C1209
0.1uF
VDDQ_4
CKE
VDDQ_4
DDR_EXT
D2
D2
VDDQ_5
VDDQ_5
E9
L2
E9
VDDQ_6
CS
VDDQ_6
DDR_EXT
C1210
0.1uF
F1
K1
F1
VDDQ_7
ODT
VDDQ_7
H2
J3
H2
C1211
0.1uF
VDDQ_8
RAS
VDDQ_8
DDR_EXT
H9
K3
H9
VDDQ_9
CAS
VDDQ_9
L3
WE
DDR_EXT
C1212
0.1uF
J1
J1
NC_1
NC_1
J9
T2
J9
NC_2
RESET
NC_2
L1
L1
NC_3
NC_3
L9
L9
NC_4
NC_4
T7
F3
T7
NC_6
DQSL
NC_6
G3
DQSL
A9
C7
A9
VSS_1
DQSU
VSS_1
B3
B7
B3
VSS_2
DQSU
VSS_2
E1
E1
VSS_3
VSS_3
G8
E7
G8
VSS_4
DML
VSS_4
J2
D3
J2
VSS_5
DMU
VSS_5
J8
J8
VSS_6
VSS_6
M1
E3
M1
VSS_7
DQL0
VSS_7
M9
F7
M9
VSS_8
DQL1
VSS_8
P1
F2
P1
VSS_9
DQL2
VSS_9
P9
F8
P9
VSS_10
DQL3
VSS_10
T1
H3
T1
VSS_11
DQL4
VSS_11
T9
H8
T9
VSS_12
DQL5
VSS_12
G2
DQL6
H7
DQL7
B1
B1
VSSQ_1
VSSQ_1
B9
D7
B9
VSSQ_2
DQU0
VSSQ_2
D1
C3
D1
VSSQ_3
DQU1
VSSQ_3
D8
C8
D8
VSSQ_4
DQU2
VSSQ_4
E2
C2
E2
VSSQ_5
DQU3
VSSQ_5
E8
A7
E8
VSSQ_6
DQU4
VSSQ_6
F9
A2
F9
VSSQ_7
DQU5
VSSQ_7
G1
B8
G1
VSSQ_8
DQU6
VSSQ_8
G9
A3
G9
VSSQ_9
DQU7
VSSQ_9
A-MA14
+1.5V_DDR
OPT
OPT
C1224
1uF
0.1uF
DDR_1600_1G_SS
IC1201
K4B1G1646G-BCK0
EAN61836301
M8
N3
VREFCA
A0
A-MA0
P7
A1
A-MA1
P3
A2
A-MA2
H1
N2
A-MA3
VREFDQ
A3
P8
A4
A-MA4
P2
A-MA5
A5
L8
R8
ZQ
A6
A-MA6
R2
A-MA7
A7
T8
A8
A-MA8
B2
R3
A-MA9
VDD_1
A9
D9
L7
VDD_2
A10/AP
A-MA10
G7
R7
A-MA11
VDD_3
A11
K2
N7
VDD_4
A12/BC
A-MA12
K8
T3
VDD_5
A13
A-MA13
N1
VDD_6
N9
M7
VDD_7
NC_5
R1
VDD_8
R9
M2
VDD_9
BA0
A-MBA0
A-MCK
N8
A-MBA1
DDR_EXT
BA1
DDR_EXT
M3
C1215
R1207
BA2
A-MBA2
0.01uF
A1
56
50V
VDDQ_1
1%
A8
J7
VDDQ_2
CK
C1
K7
DDR_EXT
VDDQ_3
CK
R1208
C9
K9
VDDQ_4
CKE
A-MCKE
56
D2
1%
VDDQ_5
A-MCKB
E9
L2
VDDQ_6
CS
A/B_DDR3_CS
F1
K1
VDDQ_7
ODT
A-MODT
+1.5V_DDR
H2
J3
VDDQ_8
RAS
A-MRASB
H9
K3
DDR_EXT
VDDQ_9
CAS
A-MCASB
L3
R1206
A-MWEB
WE
10K
J1
NC_1
J9
T2
A-MRESETB
NC_2
RESET
L1
NC_3
L9
NC_4
T7
F3
NC_6
DQSL
A-MDQSL
G3
A-MDQSLB
DQSL
A9
C7
DQSU
A-MDQSU
VSS_1
B3
B7
VSS_2
DQSU
A-MDQSUB
E1
VSS_3
G8
E7
VSS_4
DML
A-MDML
J2
D3
VSS_5
DMU
A-MDMU
J8
VSS_6
M1
E3
VSS_7
DQL0
A-MDQL0
M9
F7
A-MDQL1
VSS_8
DQL1
P1
F2
VSS_9
DQL2
A-MDQL2
P9
F8
A-MDQL3
VSS_10
DQL3
T1
H3
VSS_11
DQL4
A-MDQL4
T9
H8
A-MDQL5
VSS_12
DQL5
G2
DQL6
A-MDQL6
H7
DQL7
A-MDQL7
B1
VSSQ_1
B9
D7
VSSQ_2
DQU0
A-MDQU0
D1
C3
VSSQ_3
DQU1
A-MDQU1
D8
C8
VSSQ_4
DQU2
A-MDQU2
E2
C2
A-MDQU3
VSSQ_5
DQU3
E8
A7
VSSQ_6
DQU4
A-MDQU4
F9
A2
A-MDQU5
VSSQ_7
DQU5
G1
B8
VSSQ_8
DQU6
A-MDQU6
G9
A3
A-MDQU7
VSSQ_9
DQU7
M1A_256M_UO4
IC101
M1A_128M_UO4
IC101-*1
LGE2134(256M)
LGE2133(128M)
E11
B_DDR3_A[0]
E11
F12
A-MA0
B_DDR3_A[0]
B_DDR3_A[1]
F12
D10
B_DDR3_A[2]
A-MA1
B_DDR3_A[1]
B10
D10
B_DDR3_A[3]
E15
A-MA2
B_DDR3_A[2]
B_DDR3_A[4]
B10
B11
A-MA3
B_DDR3_A[5]
B_DDR3_A[3]
F14
E15
B_DDR3_A[6]
C11
A-MA4
B_DDR3_A[4]
B_DDR3_A[7]
B11
D14
A-MA5
B_DDR3_A[8]
B_DDR3_A[5]
A12
F14
B_DDR3_A[9]
A-MA6
B_DDR3_A[6]
F16
B_DDR3_A[10]
C11
D13
A-MA7
B_DDR3_A[7]
B_DDR3_A[11]
D15
D14
B_DDR3_A[12]
A-MA8
B_DDR3_A[8]
C12
A12
B_DDR3_A[13]
E13
A-MA9
B_DDR3_A[9]
B_DDR3_A[14]
F16
A-MA10
B_DDR3_A[10]
A9
D13
B_DDR3_BA[0]
D16
A-MA11
B_DDR3_A[11]
B_DDR3_BA[1]
D15
A10
B_DDR3_BA[2]
A-MA12
B_DDR3_A[12]
C12
A-MA13
B_DDR3_A[13]
C13
E13
B_DDR3_MCLK
B13
A-MA14
B_DDR3_A[14]
B_DDR3_MCLKZ
E17
B_DDR3_MCLKE
A9
B8
A-MBA0
B_DDR3_BA[0]
B_DDR3_ODT
C8
D16
B_DDR3_RASZ
A-MBA1
B_DDR3_BA[1]
B9
A10
B_DDR3_CASZ
A-MBA2
D11
B_DDR3_BA[2]
B_DDR3_WEZ
F10
C13
B_RESET
A-MCK
B_DDR3_MCLK
B13
D12
A-MCKB
B_DDR3_MCLKZ
B_DDR3_CS0
E17
A-MCKE
A19
B_DDR3_MCLKE
B_DDR3_DQSL
B18
B_DDR3_DQSU
B8
A-MODT
B_DDR3_ODT
C16
C8
B_DDR3_DQML
D21
A-MRASB
B_DDR3_RASZ
B_DDR3_DQMU
B9
A-MCASB
B_DDR3_CASZ
C18
D11
B_DDR3_DQSBL
C17
A-MWEB
B_DDR3_WEZ
B_DDR3_DQSBU
F10
A20
B_DDR3_DQL[0]
A-MRESETB
B_RESET
A16
B_DDR3_DQL[1]
C19
B_DDR3_DQL[2]
D12
C15
A/B_DDR3_CS
B_DDR3_DQL[3]
B_DDR3_CS0
C20
B_DDR3_DQL[4]
C14
B_DDR3_DQL[5]
A19
B21
A-MDQSL
B_DDR3_DQL[6]
B_DDR3_DQSL
B15
B18
B_DDR3_DQL[7]
A-MDQSU
B_DDR3_DQSU
F18
B_DDR3_DQU[0]
D19
B_DDR3_DQU[1]
C16
D17
B_DDR3_DQU[2]
A-MDML
B_DDR3_DQML
E21
D21
B_DDR3_DQU[3]
E19
A-MDMU
B_DDR3_DQMU
B_DDR3_DQU[4]
D20
B_DDR3_DQU[5]
D18
C18
B_DDR3_DQU[6]
F20
A-MDQSLB
B_DDR3_DQSBL
B_DDR3_DQU[7]
C17
A-MDQSUB
B_DDR3_DQSBU
E9
ZQ
A20
A-MDQL0
B_DDR3_DQL[0]
A16
A-MDQL1
B_DDR3_DQL[1]
C19
A-MDQL2
B_DDR3_DQL[2]
C15
A-MDQL3
B_DDR3_DQL[3]
C20
A-MDQL4
B_DDR3_DQL[4]
C14
A-MDQL5
B_DDR3_DQL[5]
B21
A-MDQL6
B_DDR3_DQL[6]
B15
A-MDQL7
B_DDR3_DQL[7]
F18
A-MDQU0
B_DDR3_DQU[0]
D19
A-MDQU1
B_DDR3_DQU[1]
D17
A-MDQU2
B_DDR3_DQU[2]
E21
A-MDQU3
B_DDR3_DQU[3]
E19
A-MDQU4
B_DDR3_DQU[4]
D20
A-MDQU5
B_DDR3_DQU[5]
D18
A-MDQU6
B_DDR3_DQU[6]
F20
A-MDQU7
B_DDR3_DQU[7]
E9
ZQ
R1209
240
1%
L14_CA_M1A
DDR
M1A_256M_AVS+
M1A_128M_AVS+
IC101-*2
IC101-*3
LGE2136(256M)
LGE2135(128M)
E11
E11
B_DDR3_A[0]
B_DDR3_A[0]
F12
F12
B_DDR3_A[1]
B_DDR3_A[1]
D10
D10
B_DDR3_A[2]
B_DDR3_A[2]
B10
B10
B_DDR3_A[3]
B_DDR3_A[3]
E15
E15
B_DDR3_A[4]
B_DDR3_A[4]
B11
B11
B_DDR3_A[5]
B_DDR3_A[5]
F14
F14
B_DDR3_A[6]
B_DDR3_A[6]
C11
C11
B_DDR3_A[7]
B_DDR3_A[7]
D14
D14
B_DDR3_A[8]
B_DDR3_A[8]
A12
A12
B_DDR3_A[9]
B_DDR3_A[9]
F16
F16
B_DDR3_A[10]
B_DDR3_A[10]
D13
D13
B_DDR3_A[11]
B_DDR3_A[11]
D15
D15
B_DDR3_A[12]
B_DDR3_A[12]
C12
C12
B_DDR3_A[13]
B_DDR3_A[13]
E13
E13
B_DDR3_A[14]
B_DDR3_A[14]
A9
A9
B_DDR3_BA[0]
B_DDR3_BA[0]
D16
D16
B_DDR3_BA[1]
B_DDR3_BA[1]
A10
A10
B_DDR3_BA[2]
B_DDR3_BA[2]
C13
C13
B_DDR3_MCLK
B_DDR3_MCLK
B13
B13
B_DDR3_MCLKZ
B_DDR3_MCLKZ
E17
E17
B_DDR3_MCLKE
B_DDR3_MCLKE
B8
B8
B_DDR3_ODT
B_DDR3_ODT
C8
C8
B_DDR3_RASZ
B_DDR3_RASZ
B9
B9
B_DDR3_CASZ
B_DDR3_CASZ
D11
D11
B_DDR3_WEZ
B_DDR3_WEZ
F10
F10
B_RESET
B_RESET
D12
D12
B_DDR3_CS0
B_DDR3_CS0
A19
A19
B_DDR3_DQSL
B_DDR3_DQSL
B18
B18
B_DDR3_DQSU
B_DDR3_DQSU
C16
C16
B_DDR3_DQML
B_DDR3_DQML
D21
D21
B_DDR3_DQMU
B_DDR3_DQMU
C18
C18
B_DDR3_DQSBL
B_DDR3_DQSBL
C17
C17
B_DDR3_DQSBU
B_DDR3_DQSBU
A20
A20
B_DDR3_DQL[0]
B_DDR3_DQL[0]
A16
A16
B_DDR3_DQL[1]
B_DDR3_DQL[1]
C19
C19
B_DDR3_DQL[2]
B_DDR3_DQL[2]
C15
C15
B_DDR3_DQL[3]
B_DDR3_DQL[3]
C20
C20
B_DDR3_DQL[4]
B_DDR3_DQL[4]
C14
C14
B_DDR3_DQL[5]
B_DDR3_DQL[5]
B21
B21
B_DDR3_DQL[6]
B_DDR3_DQL[6]
B15
B15
B_DDR3_DQL[7]
B_DDR3_DQL[7]
F18
F18
B_DDR3_DQU[0]
B_DDR3_DQU[0]
D19
D19
B_DDR3_DQU[1]
B_DDR3_DQU[1]
D17
D17
B_DDR3_DQU[2]
B_DDR3_DQU[2]
E21
E21
B_DDR3_DQU[3]
B_DDR3_DQU[3]
E19
E19
B_DDR3_DQU[4]
B_DDR3_DQU[4]
D20
D20
B_DDR3_DQU[5]
B_DDR3_DQU[5]
D18
D18
B_DDR3_DQU[6]
B_DDR3_DQU[6]
F20
F20
B_DDR3_DQU[7]
B_DDR3_DQU[7]
E9
E9
ZQ
ZQ
2014/06/13
12
LGE Internal Use Only
- Quick Links:
- Exploded View
Hide quick links:
Advertisement
