Page 1 User’s Manual 78K0/KC1 8-Bit Single-Chip Microcontrollers µ µ µ µ PD780111 PD780111(A) PD780111(A1) PD780111(A2) µ µ µ µ PD780112 PD780112(A) PD780112(A1) PD780112(A2) µ µ µ µ PD780113 PD780113(A) PD780113(A1) PD780113(A2) µ µ µ µ PD780114 PD780114(A) PD780114(A1) PD780114(A2) µ µ...
Page 2 [MEMO] User’s Manual U16227EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KC1 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KC1 78K/0 Series User’s Manual...
Page 7: User's Manual U16227Ej2V0Ud
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. • When using this manual as the manual for (A) grade products, (A1) grade products, and (A2) grade products: →...
Page 8 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/KC1 User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E Documents Related to Development Tools (Software) (User’s Manuals) Document Name Document No.
Page 9 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 10: Table Of Contents
Applications..........................18 Ordering Information ......................... 19 Pin Configuration (Top View)....................21 K1 Family Lineup........................23 1.5.1 78K0/Kx1 product lineup........................ 23 1.5.2 V850ES/Kx1 product lineup ......................25 Block Diagram ..........................27 Outline of Functions ........................28 CHAPTER 2 PIN FUNCTIONS ....................... 30 Pin Function List ........................
Page 11 3.3.2 Immediate addressing ........................64 3.3.3 Table indirect addressing .......................65 3.3.4 Register addressing........................65 Operand Address Addressing ....................66 3.4.1 Implied addressing .........................66 3.4.2 Register addressing........................67 3.4.3 Direct addressing..........................68 3.4.4 Short direct addressing........................69 3.4.5 Special function register (SFR) addressing ..................70 3.4.6 Register indirect addressing ......................71 3.4.7 Based addressing...........................72 3.4.8...
Page 12 5.8.4 Switching from subsystem clock to X1 input clock................122 5.8.5 Register settings ...........................123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ................124 Functions of 16-Bit Timer/Event Counter 00 ................. 124 Configuration of 16-Bit Timer/Event Counter 00..............125 Registers Controlling 16-Bit Timer/Event Counter 00 ............129 Operation of 16-Bit Timer/Event Counter 00 .................
Page 13 10.2 Configuration of Watchdog Timer..................211 10.3 Registers Controlling Watchdog Timer ................. 212 10.4 Operation of Watchdog Timer ....................214 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option ..214 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option ..........................215 10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software”...
Page 14 CHAPTER 15 INTERRUPT FUNCTIONS .................... 313 15.1 Interrupt Function Types......................313 15.2 Interrupt Sources and Configuration ..................313 15.3 Registers Controlling Interrupt Functions ................316 15.4 Interrupt Servicing Operations ....................323 15.4.1 Maskable interrupt request acknowledgment................323 15.4.2 Software interrupt request acknowledgment.................325 15.4.3 Multiple interrupt servicing ......................326 15.4.4 Interrupt request hold........................329 CHAPTER 16 KEY INTERRUPT FUNCTION ..................
Page 15 CHAPTER 22 MASK OPTIONS ......................375 µ CHAPTER 23 PD78F0114........................376 23.1 Internal Memory Size Switching Register ................377 23.2 Writing with Flash Programmer....................378 23.3 Programming Environment..................... 385 23.4 Communication Mode ......................385 23.5 Handling of Pins on Board...................... 388 23.5.1 V pin ............................388 23.5.2 Serial interface pins ........................389...
Page 16 Language Processing Software....................467 Control Software ........................468 Flash Memory Writing Tools ....................468 Debugging Tools (Hardware) ....................469 A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A ..........469 A.5.2 When using in-circuit emulator IE-78K0K1-ET................470 Debugging Tools (Software) ....................471 Embedded Software......................... 472 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ..............
Page 17: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features µ Minimum instruction execution time can be changed from high speed (0.2 s: @ 10 MHz operation with X1 µ input clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose registers: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Item Program Memory...
Page 18: Applications
CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment • System control for body electricals (power windows, keyless entry reception, etc.) • Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances • Outdoor air conditioner units •...
Page 19: Ordering Information
CHAPTER 1 OUTLINE 1.3 Ordering Information Part Number Package Quality Grade µ 44-pin plastic LQFP (10 × 10) PD780111GB-×××-8ES Standard µ 44-pin plastic LQFP (10 × 10) PD780112GB-×××-8ES Standard µ 44-pin plastic LQFP (10 × 10) PD780113GB-×××-8ES Standard µ 44-pin plastic LQFP (10 × 10) PD780114GB-×××-8ES Standard µ...
Page 20 CHAPTER 1 OUTLINE µ Mask ROM versions ( PD780111, 780112, 780113, and 780114) include mask options. When ordering, it is possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63)”.
Page 21: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 44-pin plastic LQFP (10 × 10) 44 43 42 41 40 39 38 37 36 35 34 P73/KR3 P00/TI000 IC (V P01/TI010/TO00 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 RESET P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P130 12 13 14 15 16 17 18 19 20 21 22 Cautions 1.
Page 22 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input RESET: Reset Analog reference voltage RxD0, RxD6: Receive data Analog ground SCK10: Serial clock input/output Power supply for port SI10: Serial data input Ground for port SO10: Serial data output Internally connected TI000, TI010, INTP0 to INTP5: External interrupt input...
Page 23: K1 Family Lineup
PD780122 µ Mask ROM: 8 KB, RAM: 512 bytes PD780121 78K0/KE1: 64-pin (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch) µ µ PD78F0134 Flash memory: 32 KB, RAM: 1 KB...
Page 24 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Package 30 pins 44 pins 52 pins 64 pins 80 pins − − − − − − Internal Mask ROM...
Page 25: V850Es/Kx1 Product Lineup
CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1 product lineup 80-pin plastic QFP (14 × 14) V850ES/KF1 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD703208 Mask ROM: 64 KB, RAM: 4 KB µ PD703208Y C products µ PD703209 Mask ROM: 96 KB, RAM: 4 KB µ...
Page 26 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Function Timer Serial Interface Other Part No. 8-Bit 16-Bit TMH Watch WDT CSIA UART µ PD703208 2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch –...
Page 27: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00, P01 event counter 00 TI000/P00 Port 1 P10 to P17 TOH0/P15 8-bit timer H0 Port 2 P20 to P27 TOH1/P16 Port 3 P30 to P33 8-bit timer H1 Port 6 P60 to P63 8-bit timer/...
Page 28: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) µ µ µ µ µ Item PD780111 PD780112 PD780113 PD780114 PD78F0114 Note 1 Internal memory 8 KB 16 KB 24 KB 32 KB 32 KB (flash memory) Note 1 High-speed RAM 512 bytes 1 KB 1 KB Memory space...
Page 29 CHAPTER 1 OUTLINE (2/2) µ µ µ µ µ Item PD780111 PD780112 PD780113 PD780114 PD78F0114 Vectored interrupt Internal sources External Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR3). Reset • Reset using RESET pin •...
Page 30: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 31 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Function After Reset Alternate Function P120 Port 12. Input INTP0 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. − P130 Output Port 13. Output 1-bit output-only port.
Page 32 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 P30 to P32 specified INTP4...
Page 33: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 and P01 (port 0) P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 and P01 function as a 2-bit I/O port.
Page 34: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port.
Page 35: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port.
Page 36: P120 (Port 12)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 37: Ic (Mask Rom Versions Only)
CHAPTER 2 PIN FUNCTIONS 2.2.17 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KC1 at shipment. Connect it directly to EV or V pin with the shortest possible wire in the normal operation mode.
Page 38: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 39 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A Pull-up P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 40 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Type 13-W IN/OUT   Mask   Data option   N-ch IN/OUT Output disable Data N-ch Output disable Input enable Middle-voltage input buffer Type 13-V Type 16 Feedback ...
Page 41: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space 78K0/KC1 products can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial value of the internal memory size switching register (IMS) of all 78K0/KC1 products is fixed (IMS = CFH).
Page 42 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD780111) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH 1FFFH Program area Data memory 1000H...
Page 43 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD780112) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH 3FFFH Program area Data memory 1000H...
Page 44 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD780113) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 5FFFH Program area Data memory 1000H...
Page 45 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD780114) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 7FFFH Program area Data memory 1000H...
Page 46 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Memory Map ( PD78F0114) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 7FFFH Program area Data memory 1000H...
Page 47: Internal Program Memory Space
The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KC1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number...
Page 48: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KC1 products incorporate the following internal high-speed RAMs. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal Expansion RAM µ 512 × 8 bits (FD00H to FEFFH) PD780111 µ PD780112 µ...
Page 49: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KC1, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
Page 50 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-7. Correspondence Between Data Memory and Addressing ( PD780112) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 51 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Correspondence Between Data Memory and Addressing ( PD780113) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 52 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-9. Correspondence Between Data Memory and Addressing ( PD780114) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 53 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0114) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 54: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/KC1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 55 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
Page 56 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Format of Stack Pointer SP15 SP14 SP13 SP12 SP11 SP10 SP9 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack.
Page 57 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 58: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 59: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 60 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 61 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF3CH Pull-up resistor option register 12 PU12 − √...
Page 62 Notes 1. This value varies depending on the reset source. The default value of IMS is fixed (IMS = CFH) in all 78K0/KC1 products regardless of the internal memory capacity. Therefore, set the following value to each product. Internal Memory Size Switching Register (IMS) µ...
Page 63: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 64: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 65: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 66: Operand Address Addressing
3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KC1 instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU...
Page 67: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 and RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 68: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 69: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 70: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 71: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 72: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 73: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 74: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 75: Chapter 4 Port Functions
P20 to P27 Port pins other than P20 to P27 78K0/KC1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Page 76 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Pin Name Function After Reset Alternate Function Port 0. Input TI000 2-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 77: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-3. Port Configuration Item Configuration Control registers Port mode register (PM0, PM1, PM3, PM6, PM7, PM12) Port register (P0 to P3, P6, P7, P12, P13) Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12) Ports Total: 32 (CMOS I/O: 19, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4) •...
Page 78: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
Page 79 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 80: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
Page 81 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 82 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch P12/SO10, (P12, P15) P15/TOH0 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 83 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 PU13 P-ch PORT Output latch P13/TxD6 (P13) PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 85: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-9 shows a block diagram of port 2. Figure 4-9. Block Diagram of P20 to P27 A/D converter P20/ANI0 to P27/ANI7 Read signal...
Page 86: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U16227EJ2V0UD...
Page 88: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on whether the product is a mask ROM version or a flash memory version.
Page 89: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 7 Port 7 is a 4-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P73 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
Page 90: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 91: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 13 Port 13 is a 1-bit output-only port. Figure 4-15 shows a block diagram of port 13. Figure 4-15. Block Diagram of P130 PORT Output latch P130 (P130) Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Page 92: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12) • Port registers (P0 to P3, P6, P7, P12, P13) •...
Page 93 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × TI010 Input TO00 Output × SCK10 Input Output TxD0 Output ×...
Page 94 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P3, P6, P7, P12, and P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 95 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, PU7, and PU12) These registers specify whether the on-chip pull-up resistors of P00, P01, P10 to P17, P30 to P33, P70 to P73, or P120 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, and PU12.
Page 96: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 97: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • X1 oscillator The X1 oscillator oscillates a clock of f = 2.0 to 10.0 MHz.
Page 98 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus Oscillation Main OSC Processor clock Main clock stabilization time control control register mode register select register register (PCC) (MCM) (OSTS) (MOC) OSTS2 OSTS1 OSTS0 CSS PCC2 PCC1 PCC0 MSTOP MCM0 X1 oscillation...
Page 99: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 100 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 00H Symbol <7> <6> <5> <4> PCC2 PCC1 PCC0 Note 2 Control of X1 oscillator operation Oscillation possible Oscillation stopped Subsystem clock feedback resistor selection On-chip feedback resistor used Note 3 On-chip feedback resistor not used...
Page 101 CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KC1. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in Table 5-2.
Page 102 CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 103 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
Page 104 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 105 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock.
Page 106: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 10 MHz) connected to the X1 and X2 pins. External clocks can be input to the X1 oscillator. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin.
Page 107 CHAPTER 5 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 108 CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 109: When Subsystem Clock Is Not Used
5.4.4 Ring-OSC oscillator Ring-OSC oscillator is incorporated in the 78K0/KC1. “Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)).
Page 110: Clock Generator Operation
• Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KC1, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released.
Page 111 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC X1 input clock Ring-OSC clock Subsystem clock RESET Switched by software X1 input clock Ring-OSC clock CPU clock Operation stopped: 17/f Note X1 oscillation stabilization time: 2 to 2 Note Check using the oscillation stabilization time counter status register (OSTC).
Page 112 CHAPTER 5 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively.
Page 113 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (2/4) (2) When “Ring-OSC can be stopped by software” is selected by mask option (when subsystem clock is used) Status 6 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1...
Page 114 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (3/4) (3) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is not used) HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 1 Status 2 Note 2 MCM0 = 0...
Page 115 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (4/4) (4) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is used) Status 5 CPU clock: f : Oscillation stopped : Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4...
Page 116 CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock After Supplied to Peripherals MSTOP = 0 MSTOP = 1 Note 1 Note 2 Operation Oscillator Release MCC = 0...
Page 117: Time Required To Switch Between Ring-Osc Clock And X1 Input Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 5-5).
Page 118: Time Required For Cpu Clock Switchover
CHAPTER 5 CLOCK GENERATOR 5.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 5-6).
Page 119: Clock Switching Flowchart And Register Setting
CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to X1 input clock Figure 5-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) After reset release PCC = 00H RCM = 00H ;...
Page 120: Switching From X1 Input Clock To Ring-Osc Clock
CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from X1 input clock to Ring-OSC clock Figure 5-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 121: Switching From X1 Input Clock To Subsystem Clock
CHAPTER 5 CLOCK GENERATOR 5.8.3 Switching from X1 input clock to subsystem clock Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 122: Switching From Subsystem Clock To X1 Input Clock
CHAPTER 5 CLOCK GENERATOR 5.8.4 Switching from subsystem clock to X1 input clock Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) PCC.4 (CSS) = 1 ; Subsystem clock operation MCM = 03H No: X1 oscillating MCC = 1? ;...
Page 123: Register Settings
CHAPTER 5 CLOCK GENERATOR 5.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 5-7. Clock and Register Setting Mode Setting Flag Status Flag PCC Register Register Register Register Register Register...
Page 124: Chapter 6 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
Page 125: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16 bits (TM00) Register 16-bit timer capture/compare register: 16 bits (CR000, CR010) Timer input TI000, TI010 Timer output...
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF10H, FF11H After reset: 0000H Symbol...
Page 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES001 ES000 Falling edge...
Page 128 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).
Page 129: Registers Controlling 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 The following six registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) • 16-bit timer output control register 00 (TOC00) •...
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-6.
Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00...
Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H.
Page 134 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 5. When P01 is used as the TI010 valid edge input pin, it cannot be used as the timer output (TO00), and when used as TO00, it cannot be used as the TI010 valid edge input pin. Remarks 1.
Page 135: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (2/2) (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer.
Page 137: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1>...
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Control Register Settings for PPG Output Operation (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...
Page 139 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/P00 eliminator TO00/TI010/P01 16-bit timer capture/compare register 010 (CR010) Figure 6-15. PPG Output Operation Timing Count clock M −...
Page 140: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter 16-bit timer counter 00 OVF00 (TM00) 16-bit timer capture/compare TI000 register 010 (CR010) INTTM010 Internal bus Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM00 count value TI000 pin input CR010 capture value INTTM010...
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 148: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-26 for the set value). <2> Set the count clock by using the PRM00 register. <3>...
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (2/2) (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting “10”...
Page 150: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-29 for the set value). <3>...
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.
Page 152: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as compare register CR010 used as compare register...
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR010 set value CR000 set value...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00...
Page 156 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock − − TM00 count value 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2 CR010 set value...
Page 157: Cautions For 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions for 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 158 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear &...
Page 159 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins are not acknowledged.
Page 160: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Page 161 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Note 1 Match 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)
Page 162: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 163 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
Page 164: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 165 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge (10 MHz) /2 (5 MHz) (625 kHz)
Page 166 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 167 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 168 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, set PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 169: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 170 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt acknowledged...
Page 171: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 172: Square-Wave Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 173: Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 174 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 175 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
Page 176 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 177: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 178: Chapter 8 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output • Carrier generator mode (8-bit timer H1 only) 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 179 Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 00 (CMP00) 10 (CMP10) Decoder TOH0/P15 Selector...
Page 180 Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode control 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare...
Page 181 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H Symbol...
Page 182: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 183 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 CKS01...
Page 184 CHAPTER 8 8-BIT TIMERS H0 AND H1 Remarks 1. f : X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at f = 10 MHz. Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7>...
Page 185 CHAPTER 8 8-BIT TIMERS H0 AND H1 Remarks 1. f : X1 input clock oscillation frequency 2. f : Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at f = 10 MHz, f = 240 kHz (TYP.). (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1.
Page 186: Operation Of 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 187 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 188 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 189: Operation As Pwm Output Mode
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 190 CHAPTER 8 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register.
Page 191 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 192 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 193 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 194 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 195: Carrier Generator Mode Operation (8-Bit Timer H1 Only)
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 196 CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 197 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 198 CHAPTER 8 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1.
Page 199 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
Page 200 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
Page 201 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 202: Chapter 9 Watch Timer
CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1.
Page 203 CHAPTER 9 WATCH TIMER (1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time When Operated at f = 32.768 kHz When Operated at f = 10 MHz µ...
Page 204: Configuration Of Watch Timer
CHAPTER 9 WATCH TIMER 9.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 9-3. Watch Timer Configuration Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM).
Page 205 CHAPTER 9 WATCH TIMER Figure 9-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH After reset: 00H Symbol <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (78.125 kHz) (32.768 kHz) WTM6 WTM5 WTM4...
Page 206: Watch Timer Operations
CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 207: Interval Timer Operation
CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 208: Cautions For Watch Timer
CHAPTER 9 WATCH TIMER 9.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM.
Page 209: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 18 RESET FUNCTION.
Page 210 CHAPTER 10 WATCHDOG TIMER Table 10-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f source stopped) •...
Page 211: Configuration Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 10-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 212: Registers Controlling Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 213 CHAPTER 10 WATCHDOG TIMER Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. 2.
Page 214: Operation Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 215: Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option
CHAPTER 10 WATCHDOG TIMER 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 216: Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 10 WATCHDOG TIMER 10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used.
Page 217 CHAPTER 10 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the X1 input clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 218: Watchdog Timer Operation In Halt Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 10 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 219: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7.
Page 220: Configuration Of A/D Converter
CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 11-1. Registers of A/D Converter Used on Software Item Configuration Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT)
Page 221 CHAPTER 11 A/D CONVERTER (8) AV This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential as that of the V pin even when the A/D converter is not used. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AV In the standby mode, the current flowing through the series resistor string can be reduced by lowering the voltage input to the AV pin to the AV...
Page 222: Registers Used In A/D Converter
CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The following five registers are used to control the A/D converter. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • A/D conversion result register (ADCR) •...
Page 223 CHAPTER 11 A/D CONVERTER Notes 2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that µ generates the reference voltage for boosting is controlled by ADCE, and it takes 14 s from operation µ start to operation stabilization.
Page 224 CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 11-4.
Page 225 CHAPTER 11 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB).
Page 226 CHAPTER 11 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 227: A/D Converter Operations
CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 14 s or longer. <3>...
Page 228 CHAPTER 11 A/D CONVERTER Figure 11-8. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 229: Input Voltage And Conversion Results
CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 230: A/D Converter Operation Mode
CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 231 CHAPTER 11 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 232 CHAPTER 11 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 233: How To Read A/D Converter Characteristics Table
CHAPTER 11 A/D CONVERTER 11.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 234 CHAPTER 11 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 235: Cautions For A/D Converter
CHAPTER 11 A/D CONVERTER (8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time...
Page 236 CHAPTER 11 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 11-19, to reduce noise.
Page 237 CHAPTER 11 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 238 CHAPTER 11 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 11-21 and Table 11-3.
Page 239 CHAPTER 11 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 11-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.7 V 12 kΩ...
Page 240: Chapter 12 Serial Interface Uart0
CHAPTER 12 SERIAL INTERFACE UART0 12.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 241: Configuration Of Serial Interface Uart0
CHAPTER 12 SERIAL INTERFACE UART0 12.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 12-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 242 Figure 12-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 243 CHAPTER 12 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 244: Registers Controlling Serial Interface Uart0
CHAPTER 12 SERIAL INTERFACE UART0 12.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 245 CHAPTER 12 SERIAL INTERFACE UART0 Figure 12-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 246 CHAPTER 12 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 247 CHAPTER 12 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH.
Page 248 CHAPTER 12 SERIAL INTERFACE UART0 Remarks 1. f : Frequency of base clock selected by the TPS01 and TPS00 bits XCLK0 2. f X1 input clock oscillation frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4.
Page 249: Operation Of Serial Interface Uart0
CHAPTER 12 SERIAL INTERFACE UART0 12.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 12.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 250: Asynchronous Serial Interface (Uart) Mode
CHAPTER 12 SERIAL INTERFACE UART0 12.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 251 CHAPTER 12 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 12-6 and 12-7 show the format and waveform example of the normal transmit/receive data. Figure 12-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 252 CHAPTER 12 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 253 CHAPTER 12 SERIAL INTERFACE UART0 (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 254 CHAPTER 12 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 255 CHAPTER 12 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 256: Dedicated Baud Rate Generator
CHAPTER 12 SERIAL INTERFACE UART0 12.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 257 CHAPTER 12 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 258 CHAPTER 12 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 12-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS00 Value TPS00...
Page 259 CHAPTER 12 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 260 CHAPTER 12 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 261: Chapter 13 Serial Interface Uart6
CHAPTER 13 SERIAL INTERFACE UART6 13.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 262 CHAPTER 13 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 263 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-2. LIN Reception Operation Wakeup Synchronous Synchronous Indent Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable Enable...
Page 264 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 265: Configuration Of Serial Interface Uart6
CHAPTER 13 SERIAL INTERFACE UART6 13.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 13-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 266 Figure 13-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)
Page 267 CHAPTER 13 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 268: Registers Controlling Serial Interface Uart6
CHAPTER 13 SERIAL INTERFACE UART6 13.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 269 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 270 CHAPTER 13 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 271 CHAPTER 13 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 272 CHAPTER 13 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 273 CHAPTER 13 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 274 CHAPTER 13 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 275 CHAPTER 13 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 276: Operation Of Serial Interface Uart6
CHAPTER 13 SERIAL INTERFACE UART6 13.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 277: Asynchronous Serial Interface (Uart) Mode
CHAPTER 13 SERIAL INTERFACE UART6 13.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 278 CHAPTER 13 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 PM14 UART6 Pin Function Operation TxD6/P13 RxD6/P14 Note Note Note Note × ×...
Page 279 CHAPTER 13 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-13 and 13-14 show the format and waveform example of the normal transmit/receive data. Figure 13-13. Format of Normal UART Transmit/Receive Data 1.
Page 280 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 281 CHAPTER 13 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 282 CHAPTER 13 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 283 CHAPTER 13 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 284 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-16 shows an example of the continuous transmission processing flow. Figure 13-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 285 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-17 shows the timing of starting continuous transmission, and Figure 13-18 shows the timing of ending continuous transmission. Figure 13-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 286 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 287 CHAPTER 13 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 288 CHAPTER 13 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 289 CHAPTER 13 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 290 CHAPTER 13 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 13-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to general- purpose register.
Page 291 CHAPTER 13 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 13-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 292: Dedicated Baud Rate Generator
CHAPTER 13 SERIAL INTERFACE UART6 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 293 CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 294 CHAPTER 13 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 295 CHAPTER 13 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 13-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 296 CHAPTER 13 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 297 CHAPTER 13 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 298 CHAPTER 13 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 299: Chapter 14 Serial Interface Csi10
CHAPTER 14 SERIAL INTERFACE CSI10 14.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
Page 300 CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-1. Block Diagram of Serial Interface CSI10 Internal bus Serial I/O shift Transmit buffer Output SI10/P11/R register 10 (SIO10) register 10 (SOTB10) selector SO10/P12 Output latch PM12 (P12) Output latch Transmit data controller Transmit controller Clock start/stop controller &...
Page 301: Registers Controlling Serial Interface Csi10
CHAPTER 14 SERIAL INTERFACE CSI10 14.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) • Port mode register 1 (PM1) •...
Page 302 CHAPTER 14 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) CSIC10 is used to specify the timing of the data transmission/reception and set the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 303 CHAPTER 14 SERIAL INTERFACE CSI10 (3) Port mode register 1 (PM1) PM1 is used to set port 1 input/output in 1-bit units. When using P10/SCK10 as the clock output pin of the serial interface, and P12/SO10 as the data output pin, clear PM10, PM12, and the output latches of P10 and P12 to 0.
Page 304: Operation Of Serial Interface Csi10
CHAPTER 14 SERIAL INTERFACE CSI10 14.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 14.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/T D0, P11/SI10/R D0, and P12/SO10 pins can be used as ordinary I/O port pins in this...
Page 305: 3-Wire Serial I/O Mode
CHAPTER 14 SERIAL INTERFACE CSI10 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
Page 306 CHAPTER 14 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD0/ SO10/P12 SCK10/ TxD0/P10 Note 1 Note 1 Note 1 Note 1 Note 1...
Page 307 CHAPTER 14 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10).
Page 308 CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 CSOT10 INTCSI10 CSIIF10 SI10 (input AAH)
Page 309 CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-6. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2; CKP10 = 0, DAP10 = 1 SCK10 SI10 capture SO10...
Page 310 CHAPTER 14 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 14-7.
Page 311 CHAPTER 14 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 14-8. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 ( ←...
Page 312 CHAPTER 14 SERIAL INTERFACE CSI10 (5) SO10 output The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0. Table 14-3. SO10 Output Status TRMD10 DAP10 DIR10 SO10 Output −...
Page 313: Chapter 15 Interrupt Functions
CHAPTER 15 INTERRUPT FUNCTIONS 15.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 314 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 315 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP5) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 316: Registers Controlling Interrupt Functions
CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request address generator interrupt detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 317 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 318 CHAPTER 15 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input.
Page 319 CHAPTER 15 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.
Page 320 CHAPTER 15 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
Page 321 CHAPTER 15 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP5. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 322 CHAPTER 15 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 323: Interrupt Servicing Operations
CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Servicing Operations 15.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 324 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 325: Software Interrupt Request Acknowledgment
CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 15-9.
Page 326: Multiple Interrupt Servicing
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment.
Page 327 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 328 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1 IE = 0...
Page 329: Interrupt Request Hold
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 330: Chapter 16 Key Interrupt Function
CHAPTER 16 KEY INTERRUPT FUNCTION 16.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR3). Table 16-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 331: Register Controlling Key Interrupt
CHAPTER 16 KEY INTERRUPT FUNCTION 16.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM3 bits using the KR0 to KR3 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 332: Chapter 17 Standby Function
CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function Table 17-1. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1 Note 1 Note 2...
Page 333 CHAPTER 17 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be released by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation.
Page 334: Registers Controlling Standby Function
CHAPTER 17 STANDBY FUNCTION 17.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter.
Page 335 CHAPTER 17 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock.
Page 336: Standby Function Operation
CHAPTER 17 STANDBY FUNCTION 17.2 Standby Function Operation 17.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Page 337 CHAPTER 17 STANDBY FUNCTION Table 17-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues When X1 Input Clock Oscillation Stopped When Ring-OSC When Ring-OSC When Ring-OSC When Ring-OSC...
Page 338 CHAPTER 17 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 339 CHAPTER 17 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 17-4.
Page 340 CHAPTER 17 STANDBY FUNCTION Figure 17-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating Reset Operation Status of CPU mode period stopped HALT mode Operating mode (17/f (Ring-OSC clock) Subsystem clock...
Page 341: Stop Mode
CHAPTER 17 STANDBY FUNCTION 17.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 342 CHAPTER 17 STANDBY FUNCTION (2) STOP mode release Figure 17-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Ring-OSC clock X1 input clock is selected as CPU clock HALT status X1 input clock when STOP instruction (oscillation stabilization time set by OSTS) is executed...
Page 343 CHAPTER 17 STANDBY FUNCTION Figure 17-6. STOP Mode Release by Interrupt Request Generation (2/2) (2) When Ring-OSC clock is used as CPU clock STOP instruction Standby release signal Operation Operating mode Operating mode STOP mode stopped Status of CPU (Ring-OSC clock) (Ring-OSC clock) (17/f Oscillates...
Page 344 CHAPTER 17 STANDBY FUNCTION Table 17-5. Operation in Response to Interrupt Request in STOP Mode Release Source MK×× PR×× Operation × Maskable interrupt Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
Page 345: Chapter 18 Reset Function
CHAPTER 18 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 346 Figure 18-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF Watchdog timer reset signal Clear Clear Clear Clock monitor reset signal Reset signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
Page 347 CHAPTER 18 RESET FUNCTION Figure 18-2. Timing of Reset by RESET Input Ring-OSC clock X1 input clock Operation stop Normal operation Reset period CPU clock Normal operation (17/f (Reset processing, Ring-OSC clock) (Oscillation stop) RESET Internal reset signal Delay Delay Note Hi-Z Port pin...
Page 348 CHAPTER 18 RESET FUNCTION Figure 18-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock X1 input clock STOP instruction execution Operation stop Normal Normal operation Reset period Stop status CPU clock (17/f operation (Reset processing, Ring-OSC clock) (Oscillation stop) (Oscillation stop) RESET...
Page 349 CHAPTER 18 RESET FUNCTION Table 18-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 350 CHAPTER 18 RESET FUNCTION Table 18-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Acknowledgment A/D converter Conversion result register (ADCR) Undefined Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0)
Page 351: Register For Confirming Reset Source
CHAPTER 18 RESET FUNCTION 18.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KC1. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
Page 352: Chapter 19 Clock Monitor
CHAPTER 19 CLOCK MONITOR 19.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 353: Register Controlling Clock Monitor
CHAPTER 19 CLOCK MONITOR 19.3 Register Controlling Clock Monitor Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 354: Operation Of Clock Monitor
CHAPTER 19 CLOCK MONITOR 19.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Monitor stop condition>...
Page 355 CHAPTER 19 CLOCK MONITOR Figure 19-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of Ring-OSC clock X1 input clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time) Clock supply Normal...
Page 356 CHAPTER 19 CLOCK MONITOR Figure 19-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 357 CHAPTER 19 CLOCK MONITOR Figure 19-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation operation...
Page 358 CHAPTER 19 CLOCK MONITOR Figure 19-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software Normal operation (X1 input clock or subsystem clock) CPU operation X1 input clock Ring-OSC clock Oscillation stopped Note RSTOP CLME...
Page 359: Chapter 20 Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V ) and detection voltage (V ), and generates internal reset signal when V <...
Page 360: Configuration Of Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-Clear Circuit Mask option Internal reset signal − Detection voltage source 20.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 361: Cautions For Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 362 CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-3. Example of Software Processing After Release of Reset (2/2) • Checking cause of reset Check cause of reset WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF...
Page 363: Chapter 21 Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 364: Registers Controlling Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) User’s Manual U16227EJ2V0UD...
Page 365 CHAPTER 21 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears LVIM to 00H. Figure 21-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H...
Page 366 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 21-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 367: Operation Of Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 368 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) Note 1 <1> LVIE flag Not cleared Not cleared (set by software) <3>...
Page 369 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 370 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) Note 1 <1> <9> Cleared by software LVIE flag (set by software) <3>...
Page 371: Cautions For Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 372 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 373 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-6. Example of Software Processing After Release of Reset (2/2) • Checking cause of reset Check cause of reset WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF...
Page 374 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When used as interrupt Check that “supply voltage (V ) > detection voltage (V )” in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI).
Page 375: Chapter 22 Mask Options
CHAPTER 22 MASK OPTIONS Mask ROM versions are provided with the following mask options. Power-on-clear (POC) circuit • POC cannot be used • POC used (detection voltage: V = 2.85 V ±0.15 V) Note • POC used (detection voltage: V = 3.5 V ±0.2 V) Ring-OSC •...
Page 376: Chapter 23 Μ Pd78F0114
µ CHAPTER 23 PD78F0114 µ PD78F0114 is provided as the flash memory version of the 78K0/KC1. µ µ PD78F0114 replaces the internal mask ROM of the PD780114 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 23-1 lists the differences between the µ...
Page 377: Internal Memory Size Switching Register
µ CHAPTER 23 PD78F0114 23.1 Internal Memory Size Switching Register µ PD78F0114 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved.
Page 378: Writing With Flash Programmer
µ CHAPTER 23 PD78F0114 23.2 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming µ The contents of the flash memory can be rewritten after the PD78F0114 has been mounted on the target system.
Page 379 µ CHAPTER 23 PD78F0114 µ Table 23-3. Wiring Between PD78F0114 and Dedicated Flash Programmer (2/2) (2) UART (UART0, UART6) Pin Configuration of Dedicated Flash Programmer With UART0 With UART0 + HS With UART6 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 380 µ CHAPTER 23 PD78F0114 Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 23-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (CSI10) Note (2.7 to 5.5 V) VDD2 (LVDD) 44 43 42 41 40 39 38 36 35 34...
Page 381 µ CHAPTER 23 PD78F0114 Figure 23-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (CSI10 + HS) Note (2.7 to 5.5 V) VDD2 (LVDD) 44 43 42 41 40 39 38 36 35 34 14 15 16 17 18 19 20 21 22 SO SCK /RESET V RESERVE/HS...
Page 382 µ CHAPTER 23 PD78F0114 Figure 23-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode Note (2.7 to 5.5 V) VDD2 (LVDD) 44 43 42 41 40 39 38 36 35 34 14 15 16 17 18 19 20 21 22 /RESET V RESERVE/HS WRITER INTERFACE...
Page 383 µ CHAPTER 23 PD78F0114 Figure 23-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode Note (2.7 to 5.5 V) VDD2 (LVDD) 44 43 42 41 40 39 38 36 35 34 14 15 16 17 18 19 20 21 22 /RESET V RESERVE/HS WRITER INTERFACE...
Page 384 µ CHAPTER 23 PD78F0114 Figure 23-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode Note (2.7 to 5.5 V) VDD2 (LVDD) 44 43 42 41 40 39 38 36 35 34 14 15 16 17 18 19 20 21 22 SO SCK /RESET V RESERVE/HS...
Page 385: Programming Environment
µ CHAPTER 23 PD78F0114 23.3 Programming Environment µ The environment required for writing a program to the flash memory of the PD78F0114 is illustrated below. Figure 23-7. Environment for Writing Program to Flash Memory RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 Note RESET µ...
Page 386 µ CHAPTER 23 PD78F0114 (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 23-9. Communication with Dedicated Flash Programmer (CSI10 + HS) Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD SO10 µ SO/TxD SI10 PD78F0114 Dedicated flash programmer SCK10...
Page 387 µ CHAPTER 23 PD78F0114 (5) UART6 Transfer rate: 4800 to 76800 bps Figure 23-12. Communication with Dedicated Flash Programmer (UART6) Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD TxD6 µ SO/TxD RxD6 PD78F0114 Dedicated flash programmer If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the µ...
Page 388: Handling Of Pins On Board
µ CHAPTER 23 PD78F0114 23.5 Handling of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 389: Serial Interface Pins
µ CHAPTER 23 PD78F0114 23.5.2 Serial interface pins The pins used by each serial interface are listed below. Table 23-5. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART0 TxD0, RxD0 UART0 + HS...
Page 390 µ CHAPTER 23 PD78F0114 (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
Page 391: Reset Pin
µ CHAPTER 23 PD78F0114 23.5.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.
Page 392: Programming Method
µ CHAPTER 23 PD78F0114 23.6 Programming Method 23.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 23-17. Flash Memory Manipulation Procedure Start Flash memory programming pulse supply mode is set Selecting communication mode Manipulate flash memory End? User’s Manual U16227EJ2V0UD...
Page 393: Flash Memory Programming Mode
µ CHAPTER 23 PD78F0114 23.6.2 Flash memory programming mode µ To rewrite the contents of the flash memory by using the dedicated flash programmer, set the PD78F0114 in the flash memory programming mode. To set the mode, set the V pin and clear the reset signal.
Page 394: Communication Commands
µ CHAPTER 23 PD78F0114 23.6.4 Communication commands µ PD78F0114 communicates with the dedicated flash programmer by using commands. The signals sent from µ µ the flash programmer to the PD78F0114 are called commands, and the commands sent from the PD78F0114 to the dedicated flash programmer are called response commands.
Page 395: Chapter 24 Instruction Set
CHAPTER 24 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KC1 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 24.1 Conventions Used in Operation List 24.1.1 Operand identifiers and specification methods...
Page 396: Description Of Operation Column
CHAPTER 24 INSTRUCTION SET 24.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 397: Operation List
CHAPTER 24 INSTRUCTION SET 24.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte A ←...
Page 398 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 399 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 400 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 401 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 402 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 403 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 404 CHAPTER 24 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 405: Instructions Listed By Addressing Type
CHAPTER 24 INSTRUCTION SET 24.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
Page 406 CHAPTER 24 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 407 CHAPTER 24 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U16227EJ2V0UD...
Page 408: (Standard Products, (A) Grade Products)
CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ Target products: PD780111, 780112, 780113, 780114, 78F0114, 780111(A), 780112(A), 780113(A), 780114(A), 78F0114(A) Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +0.3 −0.3 to +0.3 −0.3 to V...
Page 409: Chapter 25 Electrical Specifications
CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Notes 1. Must be 6.5 V or lower. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. • When supply voltage rises µ...
Page 410 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 411 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Subsystem Clock Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions...
Page 412 The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KC1 so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Page 413 The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KC1 so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Page 414 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (1/4) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 415 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (2/4) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 416 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ DC Characteristics (3/4): PD78F0114, 78F0114(A) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 417 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ DC Characteristics (4/4): PD780111, 780112, 780113, 780114, 780111(A), 780112(A), 780113(A), 780114(A) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V)
Page 418 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V (1) Basic operation (T = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 419 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V (2) Serial interface (T = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 420 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 TI00, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL...
Page 421 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 User’s Manual U16227EJ2V0UD...
Page 422 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 423 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 Note 1 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0...
Page 424 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ Flash Memory Programming Characteristics: PD78F0114, 78F0114(A) = +10 to +60°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (1) Write erase characteristics Parameter Symbol...
Page 425 CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit µ ↑ to V ↑ Set time from V µ ↑ to RESET↑ Release time from V pulse input start time from RESET↑ µ...
Page 426: Chapter 26 Electrical Specifications ((A1) Grade Products)
CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ Target products: PD780111(A1), 780112(A1), 780113(A1), 780114(A1), 78F0114(A1) Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +0.3 −0.3 to +0.3 −0.3 to V Note 1 + 0.3...
Page 427 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Notes 1. Must be 6.5 V or lower. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. • When supply voltage rises µ...
Page 428 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions...
Page 429 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN.
Page 430 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (1/6): PD78F0114(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 431 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (2/6): PD78F0114(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 432 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (3/6): PD78F0114(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 433 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (4/6): PD780111(A1), 780112(A1), 780113(A1), and 780114(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 434 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (5/6): PD780111(A1), 780112(A1), 780113(A1), and 780114(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 435 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (6/6): PD780111(A1), 780112(A1), 780113(A1), and 780114(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 436 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Characteristics (1) Basic operation = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 437 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) vs. V (X1 Input Clock Operation) 20.0 16.0 10.0 Guaranteed operation range 0.238 Supply voltage V User’s Manual U16227EJ2V0UD...
Page 438 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial interface = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note = EV = EV = AV = 0 V) µ = −40 to +110°C: Note T PD780111(A1), 780112(A1), 780113(A1), 780114(A1) = −40 to +105°C:...
Page 439 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 TI00, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH...
Page 440 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 User’s Manual U16227EJ2V0UD...
Page 441 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 442 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) = −40 to +110°C Note 1 LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.52 LVI0 4.32 LVI1 4.12 LVI2 3.92 LVI3 3.72 LVI4 Note 2 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0...
Page 443 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ Flash Memory Programming Characteristics: PD78F0114(A1) = +10 to +60°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) (1) Write erase characteristics Parameter Symbol Conditions...
Page 444 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit µ ↑ to V ↑ Set time from V µ ↑ to RESET↑ t Release time from V pulse input start time from RESET↑...
Page 445: Chapter 27 Electrical Specifications ((A2) Grade Products)
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) µ Target products: PD780111(A2), 780112(A2), 780113(A2), 780114(A2) Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +0.3 −0.3 to +0.3 −0.3 to V Note + 0.3 −0.3 to +0.3...
Page 446 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 447 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP.
Page 448 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (1/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 449 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 450 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (3/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply X1 crystal = 8.38 MHz...
Page 451 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Characteristics (1) Basic operation = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 452 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) vs. V (X1 Input Clock Operation) 20.0 16.0 10.0 Guaranteed operation range 0.238 Supply voltage V User’s Manual U16227EJ2V0UD...
Page 453 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Serial interface = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 454 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 TI00, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH...
Page 455 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 User’s Manual U16227EJ2V0UD...
Page 456 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 457 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) = −40 to +125°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.56 LVI0 4.36 LVI1 4.16 LVI2 3.96 LVI3 3.76 LVI4 Note 1 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0 Note 2...
Page 458: Chapter 28 Package Drawing
CHAPTER 28 PACKAGE DRAWING 44 PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS NOTE 12.0±0.2 10.0±0.2 Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. 10.0±0.2 12.0±0.2 +0.08 0.37 −0.07 0.20 0.8 (T.P.) 1.0±0.2...
Page 459: Chapter 29 Recommended Soldering Conditions
CHAPTER 29 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website.
Page 460 CHAPTER 29 RECOMMENDED SOLDERING CONDITIONS Table 29-1. Surface Mounting Type Soldering Conditions (2/2) µ PD78F0114M1GB-8ES, 78F0114M2GB-8ES, 78F0114M3GB-8ES, 78F0114M4GB-8ES, 78F0114M5GB-8ES, µ 78F0114M6GB-8ES, 78F0114M1GB(A)-8ES, 78F0114M2GB(A)-8ES, 78F0114M3GB(A)-8ES, µ 78F0114M4GB(A)-8ES, 78F0114M5GB(A)-8ES, 78F0114M6GB(A)-8ES, 78F0114M1GB(A1)-8ES, µ 78F0114M2GB(A1)-8ES, 78F0114M5GB(A1)-8ES, 78F0114M6GB(A1)-8ES Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max.
Page 461: Chapter 30 Cautions For Wait
CHAPTER 30 CAUTIONS FOR WAIT 30.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 462: Peripheral Hardware That Generates Wait
CHAPTER 30 CAUTIONS FOR WAIT 30.2 Peripheral Hardware That Generates Wait Table 30-1 lists the registers that issue a wait when accessed by the CPU, and the number of CPU wait clocks. Table 30-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 463: Example Of Wait Occurrence
CHAPTER 30 CAUTIONS FOR WAIT 30.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 464: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KC1. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 465 The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately. User’s Manual U16227EJ2V0UD...
Page 466 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78K0K1-ET Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 467: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 468: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT compatibles BB13 Windows (English version) AB17...
Page 469: Debugging Tools (Hardware)
IE-78K0-NS-PA This board is connected to the IE-78K0-NS to expand its functions. Adding this board Performance board adds a coverage function and enhances debugging functions such as tracer and timer functions.
Page 470: When Using In-Circuit Emulator Ie-78K0K1-Et
The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K0/Kx1 product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine.
Page 471: Debugging Tools (Software)
Windows-based software. (supporting in-circuit emulators It has improved C-compatible debugging functions and can display the results of tracing IE-78K0-NS, IE-78K0-NS-A, and with the source program using an integrating window function that associates the source IE-78K0K1-ET) program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately).
Page 472: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software µ RX78K0 The RX78K0 is a real-time OS conforming to the ITRON specifications. Real-time OS A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780114) (both sold separately).
Page 473: Appendix B Notes On Target System Design
Design your system making allowances for conditions such as the shape of parts mounted on the target system, as shown below. Figure B-1. Distance Between IE System and Conversion Adapter In-circuit emulator IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET Target system Emulation board...
Page 474 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System Emulation board IE-780148-NS-EM1 Emulation probe NP-44GB-TQ 23 mm 11 mm Conversion adapter TGB-044SAP 10 mm 40 mm 34 mm Target system Remark The NP-44GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. The TGB-044SAP is a product of TOKYO ELETECH CORPORATION.
Page 475: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR) ........................225 A/D converter mode register (ADM)..........................222 Analog input channel specification register (ADS) ......................224 Asynchronous serial interface control register 6 (ASICL6)..................274 Asynchronous serial interface operation mode register 0 (ASIM0) ................244 Asynchronous serial interface operation mode register 6 (ASIM6) ................268 Asynchronous serial interface reception error status register 0 (ASIS0)..............246...
Page 476 APPENDIX C REGISTER INDEX Interrupt request flag register 0H (IF0H) ........................318 Interrupt request flag register 0L (IF0L)........................318 Interrupt request flag register 1L (IF1L)........................318 Key return mode register (KRM) ..........................331 Low-voltage detection level selection register (LVIS)....................366 Low-voltage detection register (LVIM).........................365 Main clock mode register (MCM) ..........................102 Main OSC control register (MOC) ..........................103 Oscillation stabilization time counter status register (OSTC)................104, 334 Oscillation stabilization time select register (OSTS)....................105, 335...
Page 477 APPENDIX C REGISTER INDEX Receive buffer register 6 (RXB6) ..........................267 Reset control flag register (RESF) ..........................351 Ring-OSC mode register (RCM) ..........................101 Serial clock selection register 10 (CSIC10).........................302 Serial I/O shift register 10 (SIO10) ..........................300 Serial operation mode register 10 (CSIM10).......................301 16-bit timer capture/compare register 000 (CR000)....................126 16-bit timer capture/compare register 010 (CR010)....................128 16-bit timer counter 00 (TM00)............................126...
Page 478: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register .........................225 ADM: A/D converter mode register........................222 ADS: Analog input channel specification register .....................224 ASICL6: Asynchronous serial interface control register 6..................274 ASIF6: Asynchronous serial interface transmission status register 6 ..............271 ASIM0:...
Page 479 APPENDIX C REGISTER INDEX MCM: Main clock mode register ........................102 MK0H: Interrupt mask flag register 0H ........................319 MK0L: Interrupt mask flag register 0L.........................319 MK1L: Interrupt mask flag register 1L.........................319 MOC: Main OSC control register ........................103 OSTC: Oscillation stabilization time counter status register ................104, 334 OSTS: Oscillation stabilization time select register ..................105, 335 Port register 0............................94...
Page 480 APPENDIX C REGISTER INDEX TCL50: Timer clock selection register 50 ......................164 TCL51: Timer clock selection register 51 ......................164 TM00: 16-bit timer counter 00..........................126 TM50: 8-bit timer counter 50..........................162 TM51: 8-bit timer counter 51..........................162 TMC00: 16-bit timer mode control register 00 .......................129 TMC50: 8-bit timer mode control register 50 ......................166 TMC51:...
Page 481: Appendix D Revision History
APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/3) Page Description Throughout Addition of products µ PD78F0114(A1), 780111(A2), 780112(A2), 780113(A2), 780114(A2) Modification of names of the following special function registers (SFRs) • Ports 0 to 3, 6, 7, 12, and 13 → Port registers 0 to 3, 6, 7, 12, and 13 p.21 Addition of Caution 3 to 1.4 Pin Configuration (Top View) p.23...
Page 482 APPENDIX D REVISION HISTORY (2/3) Page Description p.160 Revision of CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 p.178 Revision of CHAPTER 8 8-BIT TIMERS H0 AND H1 p.202 Modification of Figure 9-1 Watch Timer Block Diagram p.208 Addition of Figure 9-4 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) p.219 Revision of CHAPTER 11 A/D CONVERTER...
Page 483 APPENDIX D REVISION HISTORY (3/3) Page Description p.375 Addition of Note to description in CHAPTER 22 MASK OPTIONS µ p.376 Revision of CHAPTER 23 PD78F0114 (no modification of 23.1 Internal Memory Size Switching Register) p.403 Partial modification of operation of “RETI” in 24.2 Operation List p.408 Revision of CHAPTER 25 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

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78kc1

NEC 78K0 User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 00

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 8-Bit Timers H0 and H1

Chapter 9 Watch Timer

Chapter 10 Watchdog Timer

Chapter 11 A/D Converter

Chapter 12 Serial Interface Uart0

Chapter 13 Serial Interface Uart6

Chapter 14 Serial Interface Csi10

Chapter 15 Interrupt Functions

Chapter 16 Key Interrupt Function

Chapter 17 Standby Function

Chapter 18 Reset Function

Chapter 19 Clock Monitor

Chapter 20 Power-On-Clear Circuit

Chapter 21 Low-Voltage Detector

Chapter 22 Mask Options

CHAPTER 23 Μ PD78F0114

Chapter 24 Instruction Set

Chapter 25 Electrical Specifications

Chapter 26 Electrical Specifications ((A1) Grade Products)

Chapter 27 Electrical Specifications ((A2) Grade Products)

Chapter 28 Package Drawing

Chapter 29 Recommended Soldering Conditions

Chapter 30 Cautions for Wait

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

Appendix D Revision History

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Summary of Contents for NEC 78K0